AMD's latest CPU is simply a shrunken Epyc optimized for power-limited and thermally challenging telco and unreality separator deployments.
Code named "Siena" nan House of Zen's 8004-series processors are nan last introduction successful nan chipmaker's Epyc 4 roadmap, which already includes general-purpose, high-performance compute, and cloud-optimized CPUs.
AMD envisions Siena being deployed successful a assortment of environments ranging from mill floors and distant offices to telecom guidelines stations and distant datacenters. These environments tin beryllium rather challenging compared to nan emblematic climate-controlled datacenter wherever sound aliases powerfulness depletion aren't arsenic large a concern, Lynn Comp, VP of server merchandise and exertion trading astatine AMD, explained successful a briefing up of nan launch.
Because of this, astir each facet of nan spot – including halfway count, IO, memory, and moreover its socket – has been trim down to maximize powerfulness efficiency, thermals, and minimize its footprint.
Under nan hood, we spot a acquainted statement of compute chiplets surrounding a cardinal IO die. In fact, Siena uses nan aforesaid chiplets arsenic we saw successful AMD's cloud-native Bergamo Epycs successful June. The quality is wherever that spot supported up to 8 compute dies, Siena's smaller SP6 socket tin only accommodate four.
Like Bergamo, each of these halfway analyzable dies (CCDs) person up to 16 of AMD's miniaturized Zen 4c cores. These cores waste and acquisition top-end capacity for a 35 percent smaller area and improved ratio compared to nan cores recovered successful AMD's general-purpose Genoa Epycs introduced past fall.
These cores, while smaller, are still based connected nan aforesaid instruction group architecture and connection each of nan aforesaid features arsenic AMD's full-fat Zen 4 cores.
When each 4 CCDs connected nan package are populated, nan spot tin beryllium configured pinch up to 64 cores and 128 threads. However, for little compute-intensive workloads, nan spot tin beryllium configured pinch arsenic fewer arsenic 8 cores. We're told this is achieved utilizing a azygous compute dice pinch half of nan cores disabled. This whitethorn look for illustration an overseas prime considering AMD already has higher capacity eight-core CCDs fresh to go, but Mark Bode, elder head of server merchandise guidance astatine AMD, told america us nan determination to instrumentality pinch Zen 4c cores was made to prioritize powerfulness efficiency.
AMD's edge-optimized Epycs tin beryllium had pinch betwixt 8 and 64 Zen 4c cores
Despite nan configuration, timepiece speeds are really rather accordant crossed nan full merchandise stack, pinch guidelines clocks of 2-2.65GHz and boost clocks of 3-3.1GHz.
The aforesaid can't beryllium said of powerfulness consumption, which scales proportionately pinch halfway count from a minimum configurable thermal creation powerfulness (TDP) of 70 watts connected AMD's eight-core version to up to 225 watts connected nan top-specced SKU. That's rather nan powerfulness savings compared to AMD's Genoa and Bergamo Epycs, which tin easy apical 400 watts nether afloat load.
In summation to their comparatively debased TDP, AMD besides offers web instrumentality building strategy (NEBS) compliant versions of each chip, which are designed to run successful much utmost somesthesia conditions ranging from a frigid -5°C to a sweltering 85°C.
The fat-trimming is astir evident successful nan representation and IO departments. The spot is constricted to six DDR5 channels and 96 PCIe 5.0 lanes compared to 12 channels and 128 lanes connected nan remainder of nan Epyc 4 lineup. What's more, nan spot only supports single-socket configurations.
This intends Siena is constricted to 1.152TB of representation capacity. However, if that's excessively confining, nan spot does person 48 CXL 1.1 lanes, which support representation description modules, for illustration we've seen from Samsung, Micron, aliases Astera Labs. These modules let you to widen nan representation footprint of a strategy beyond nan CPU's maximum capacity astatine nan disbursal of somewhat higher entree latencies, usually astir 1 NUMA hop.
- The early of nan unreality judge looks for illustration it'll beryllium paved successful moreover much civilization silicon
- d-Matrix bets connected in-memory compute to undercut Nvidia successful smaller AI models
- Intel shows disconnected 8-core, 528-thread processor pinch 1TB/s of co-packaged optics
- Google throws down gauntlet pinch first compute instances powered by AmpereOne chips
Despite a dense accent connected little powerfulness consumption, AMD insists its 8004-series chips are still much than tin of going toe-to-toe pinch Intel's Sapphire Rapids Xeon Scalable Processors.
AMD besides claims its chips are up to doubly arsenic businesslike successful nan SPECpower capacity per watt benchmark and up to 16 percent faster successful video-encoding workloads. However, drawback a atom of brackish while we hold for independent benchmarks.
At launch, AMD highlighted 3 OEM systems it argues exemplify Siena's flexibility: a Dell PowerEdge container designed for scale-out instrumentality workloads, a Lenovo ThinkEdge strategy optimized for separator AI and information analytics, and a Supermicro chassis tuned for separator and telco-datacenter deployments.
The chips person besides caught nan attraction of Microsoft, which successful a connection highlighted nan imaginable for customers successful unit aliases manufacturing to tally Azure services astatine nan edge.
AMD's Siena processors are disposable now pinch 1,000-unit pricing ranging from $490 to $5,450 a portion depending connected nan SKU. ®