Intel has expanded its FPGA line-up pinch cost-optimized offerings, unfastened originated nan charismatic merchandise of its package stack, and added a free RISC-V processor design, among different updates.
The Santa Clara chipmaker said it is broadening nan Agilex FPGA portfolio to meet an accrued request for customized workloads – including, inevitably, AI processing – and to connection customers a much broad line-up.
Among nan caller arrivals are products successful nan Agilex 3 instrumentality family, described by Intel arsenic powerfulness and cost-optimized FPGAs disposable successful compact shape factors. This instrumentality family was announced by nan institution earlier this twelvemonth arsenic nan lowest rung of nan Agilex portfolio beneath nan Agilex 5, 7 and 9 lines, but specifications were not disclosed astatine nan time.
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The Agilex 3 family will initially comprise nan B-Series and C-Series devices. B-Series FPGAs person higher I/O density successful smaller shape factors, and target applications specified arsenic committee and strategy management, including server level management, Intel said. The C-Series person further capabilities for analyzable programmable logic devices (CPLD) and different FPGA applications crossed vertical markets.
Intel is besides moving to present Agilex 5 E-Series devices arsenic portion of its early entree program, sampling to early entree customers from Q4 2023, pinch broader shipments successful Q1 2024. These caller additions to nan Agilex 5 family are intended to present amended capacity per watt than rival FPGAs, acknowledgment to nan Intel 7 process node exertion which was optimized for this.
The chipmaker declared that it has taken its AI tensor artifact from nan erstwhile procreation high-end offerings and is making this disposable connected nan mid-range Agilex 5 family arsenic an effort to make these much charismatic for separator AI applications. Simics – a complete strategy simulator for pre-silicon and post-silicon package development, testing, and strategy integration – is promised for Agilex 5 successful Q4 2023.
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On nan package side, Intel's Open FPGA Stack (OFS) is officially disposable arsenic unfastened source, providing developers pinch afloat entree to nan hardware code, package code, and method documentation. OFS is intended arsenic a communal model for FPGA development, combining reference codification libraries and upstreamed, unfastened root kernel drivers for Linux.
OFS supports Intel Agilex and Stratix 10 FPGAs, and nan institution said that partners specified arsenic BittWare, Hitek Systems, and SigmaX person deployable OFS-based offerings available.
Also announced is simply a caller personnel of Intel's Nios V processor IP designs, which are based connected nan unfastened modular RISC-V architecture. The Nios V/c is simply a compact microcontroller that is disposable astatine nary costs for inclusion successful customer FPGA implementations. It will besides target each devices supported successful nan Quartus Prime Pro programmable logic instrumentality creation software, Intel said.
All of these latest products and technologies are group to beryllium showcased astatine Intel's FPGA Technology Day (IFTD) successful San Jose connected September 18.
"We're eager to stock this caller FPGA line-up pinch customers and partners astatine nan yearly IFTD arena and to item nan opportunities these offerings will accelerate successful programmable innovations," Shannon Poulin, firm VP and GM of Programmable Solutions Group, said successful a statement. ®