Bad news for anyone looking to get their hands connected Nvidia's apical specced GPUs, specified arsenic nan A100 aliases H100: it's not going to get immoderate easier to root nan parts until astatine slightest nan extremity of 2024, TSMC has warned.
The problem, it seems, isn't that TSMC – which fabricates not conscionable those GPUs for Nvidia but besides components for AMD, Apple, and galore others – can't make capable chips. Rather, a deficiency of precocious packaging capacity utilized to stitch nan silicon together is holding up production, TSMC president Mark Liu told Nikkei Asia.
According to Liu, TSMC is only capable to meet astir 80 percent of request for its spot connected wafer connected substrate (CoWoS) packaging technology. This is utilized successful immoderate of nan astir precocious chips connected nan marketplace coming – peculiarly those that trust connected high-bandwidth representation (HBM) which is perfect for AI workloads.
Liu expects this is simply a impermanent bottleneck successful nan accumulation of machine-learning accelerators and that further CoWoS capacity should travel online wrong a twelvemonth and a half. Incidentally, TSMC precocious announced plans to expand its precocious packaging capacity successful Taiwan pinch a $3 cardinal installation astatine nan Tongluo Science Park successful Miaoli County.
Until TSMC tin bring further capacity online, Nvidia's H100 and older A100 – which powerfulness galore celebrated generative AI models, specified arsenic GPT-4 – are astatine nan bosom of this shortage. However, it's not conscionable Nvidia. AMD's upcoming Instinct MI300-series accelerators – which it showed off during its Datacenter and AI arena successful June – make extended usage of CoWoS packaging technology.
AMD's MI300A APU is presently sampling pinch customers and is slated to power Lawrence Livermore National Laboratory's El Capitan system, while nan MI300X GPU is owed to commencement making its measurement into customers' hands successful Q3.
We've reached retired to AMD for remark connected whether nan shortage of CoWoS packaging capacity could effect readiness of nan spot and we'll fto you cognize if we perceive thing back.
- After grounded takeover, Intel and Tower Semi aren't giving up connected nan relationship
- Rapidus ramps arsenic building originates connected 2nm wafer fab
- China cooks covert chips, recruits world geeks to dodge US restrictions
- Our AI wont is already changing nan measurement we build datacenters
It's worthy noting that TSMC's CoWoS isn't nan only packaging tech retired there. Samsung, which is rumored to prime up immoderate of nan slack for nan accumulation of Nvidia GPUs, has I-Cube and H-Cube for 2.5D packaging and X-Cube for 3D packaging.
Intel, meanwhile, packages respective of nan chiplets utilized successful its Ponte Vecchio GPU Max cards, but doesn't trust connected CoWoS tech to stitch them together. Chipzilla has developed its ain precocious packaging tech, which tin activity pinch chips from different fabs aliases process nodes. It's called embedded multi-die interconnect span (EMIB) for 2.5D packaging and Foveros for vertically stacking chiplets connected apical of 1 another. ®